For instance, an electric resistivity of a silicon crystal substrate must be extremely low in the case of an epitaxial silicon wafer for a power MOS transistor. In order to reduce an electric resistivity of a silicon crystal substrate to a satisfactory extent, arsenic (As) and antimony (Sb) are doped as an n-type dopant for adjusting a resistivity into molten silicon in a pulling step of a silicon crystal ingot that is a raw material of a wafer (that is, in growing a silicon crystal). The above technique is publicly known. However, since the above dopant is extremely easily vaporized, it is difficult to fully increase a dopant concentration in a silicon crystal, whereby it is difficult to manufacture a silicon crystal substrate that is provided with a low resistivity that is a required degree.
Consequently, a silicon crystal substrate into which phosphorus (P) has been doped at a high concentration as an n-type dopant that is provided with a characteristic of a low volatility and in which an electric resistivity is extremely low is being used.
However, in the case in which a silicon epitaxial layer is formed on a silicon crystal substrate into which phosphorus has been doped at a high concentration, a dislocation defect (a misfit dislocation) caused by a difference of a concentration of phosphorus at an interfacial part between a silicon crystal substrate and a silicon epitaxial layer occurs unfortunately. A misfit dislocation is propagated from an interfacial part of a silicon crystal substrate to a surface of a silicon epitaxial layer and is visually observed as a congestion of long and thin lines. The misfit dislocation results in a decrease in an electrical performance of a semiconductor device. A cause of the misfit dislocation is that an atomic radius of phosphorus is 1.10 A (angstrom) that is extremely smaller than an atomic radius of silicon which is 1.17 A, and a great difference of a covalent radius of the both sides causes an unnecessary strain in a crystal. (Since an atomic radius of arsenic is 1.18 A that is fairly close to an atomic radius of silicon, a misfit dislocation less occurs.)
In order to solve the above problem, germanium (Ge) of which an atomic radius is 1.22 A that is larger than that of silicon is doped simultaneously with phosphorus in a pulling step of a silicon single crystal ingot. By this process, a strain of a silicon crystal lattice caused by phosphorus is relaxed by germanium and an occurrence of a misfit dislocation is suppressed (see Patent Literature 1).
An epitaxial growth occurs at a high temperature for an epitaxial wafer. Consequently, an oxygen precipitate (BMD) and an oxygen precipitation nucleus that have been formed in a crystal in a growing stage of a silicon single crystal ingot are extinguished by a high-temperature heat treatment, whereby a gettering ability is lower unfortunately.
As a gettering method as a countermeasure for resolving a gettering shortage, an IG (intrinsic gettering) method and an EG (extrinsic gettering) method are publicly known (see Non Patent Literature 1).
For instance, a technique for executing an oxygen precipitation nucleus formation heat treatment to a wafer to increase an oxygen precipitation nucleus density and for executing an epitaxial growth is publicly known (see Patent Literature 2).
Moreover, a technique for executing a poly back seal (PBS) method before an epitaxial growth treatment is publicly known (see Patent Literature 3 and Patent Literature 4). The poly back seal (PBS) method is an example of the EG method in which a polysilicon layer is formed on the rear face of a wafer and a strain field and a lattice mismatch that occur at an interface with a substrate are utilized.